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If a state machine is defined in the source HDL code, it can be rendered as a state diagram and other nonstructural HDL can be displayed as a flow chart. Structural HDL views can be rendered as a graphical block diagram or IBD view. You can display the structure and hierarchy below any design object and compile VHDL or Verilog for individual views or hierarchies. You can explore the logical or physical design objects defined by the source HDL including any associated side data objects. The main design manager window provides library management, data exploration, and design flow control facilities. The design data is maintained as source VHDL or Verilog files which can be created or edited using HDL text or graphical editors. The HDL Designer Series tools provide a highly automated environment for managing andexploring HDL designs.
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